Principles and structures of FPGAs / (Record no. 33771)

MARC details
000 -LEADER
fixed length control field 07455cam a2200721Ia 4500
001 - CONTROL NUMBER
control field on1050602735
003 - CONTROL NUMBER IDENTIFIER
control field OCoLC
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20210825161851.0
006 - FIXED-LENGTH DATA ELEMENTS--ADDITIONAL MATERIAL CHARACTERISTICS
fixed length control field m d
007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION
fixed length control field cr |n|||||||||
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 180907s2018 si o 000 0 eng d
040 ## - CATALOGING SOURCE
Original cataloging agency YDX
Language of cataloging eng
Transcribing agency YDX
Modifying agency N$T
-- GW5XE
-- YDX
-- N$T
-- EBLCP
-- NLE
-- UPM
-- OCLCF
019 ## -
-- 1055592245
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9789811308246
Qualifying information (electronic bk.)
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9811308241
Qualifying information (electronic bk.)
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9789811308239
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
Canceled/invalid ISBN 9811308233
024 7# - OTHER STANDARD IDENTIFIER
Standard number or code 10.1007/978-981-13-0824-6
Source of number or code doi
035 ## - SYSTEM CONTROL NUMBER
System control number 1884181
-- (N$T)
035 ## - SYSTEM CONTROL NUMBER
System control number (OCoLC)1050602735
Canceled/invalid control number (OCoLC)1055592245
050 #4 - LIBRARY OF CONGRESS CALL NUMBER
Classification number TK7895.G36
Item number P75 2018
072 #7 - SUBJECT CATEGORY CODE
Subject category code TEC
Subject category code subdivision 009070
Source bisacsh
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYF
Source bicssc
072 #7 - SUBJECT CATEGORY CODE
Subject category code UYF
Source thema
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.39/5
Edition number 23
049 ## - LOCAL HOLDINGS (OCLC)
Holding library MAIN
245 00 - TITLE STATEMENT
Title Principles and structures of FPGAs /
Statement of responsibility, etc. Hideharu Amano, editor.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Singapore :
Name of publisher, distributor, etc. Springer,
Date of publication, distribution, etc. c2018.
300 ## - PHYSICAL DESCRIPTION
Extent 1 online resource
336 ## - CONTENT TYPE
Content type term text
Content type code txt
Source rdacontent
337 ## - MEDIA TYPE
Media type term computer
Media type code c
Source rdamedia
338 ## - CARRIER TYPE
Carrier type term online resource
Carrier type code cr
Source rdacarrier
347 ## - DIGITAL FILE CHARACTERISTICS
File type text file
Encoding format PDF
Source rda
588 0# - SOURCE OF DESCRIPTION NOTE
Source of description note Online resource; title from PDF title page (EBSCO, viewed September 18, 2018)
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Intro; Preface; Contents; Contributors; 1 Basic Knowledge to Understand FPGAs; 1.1 Logic Circuits; 1.1.1 Logic Algebra; 1.1.2 Logic Equation; 1.1.3 Truth Table; 1.1.4 Combinational Circuits; 1.1.5 Sequential Circuits; 1.2 Synchronous Logic Design; 1.2.1 Flip-Flop; 1.2.2 Setup Time and Hold Time; 1.2.3 Timing Analysis; 1.2.4 Single-Clock Synchronous Circuits; 1.3 Position and History of FPGAs; 1.3.1 The Position of FPGA; References; 2 What Is an FPGA?; 2.1 Components of an FPGA; 2.2 Programming Technology; 2.2.1 Flash Memory; 2.3 Antifuse Technology; 2.3.1 Static Memory Technology
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 2.3.2 Summary of Programming Technology2.4 Logic Circuit Representation of FPGA; 2.4.1 Circuit Implementation on FPGA; 2.4.2 Logical Expression by Product Term; 2.4.3 Logical Expression by Lookup Table; 2.4.4 Structure of Lookup Table; 2.4.5 Logical Expression by Other Methods; References; 3 FPGA Structure; 3.1 Logic Block; 3.1.1 Performance Trade-Off of Lookup Tables; 3.1.2 Dedicated Carry Logic; 3.2 Logic Cluster; 3.3 Adaptive LUT; 3.3.1 Altera Stratix II; 3.3.2 Xilinx Virtex 5; 3.4 Routing Part; 3.4.1 Global Routing Architecture; 3.4.2 Detailed Routing Architecture
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 3.4.3 Wire Segment Length3.4.4 Structure of Routing Switch; 3.5 Switch Block; 3.5.1 Switch Block Topology; 3.5.2 Multiplexer Structure; 3.6 Connection Block; 3.7 I/O Block; 3.8 DSP Block; 3.8.1 Example Structure of a DSP Block; 3.8.2 Arithmetic Granularity; 3.8.3 Usage of DSP Blocks; 3.9 Hard Macros; 3.9.1 Interface Circuits as Hard Macros; 3.9.2 Hard-Core Processors; 3.10 Embedded Memory; 3.10.1 Memory Blocks as Hard Macros; 3.10.2 Memory Using LUTs in Logic Blocks; 3.10.3 Usage of Embedded Memory; 3.11 Configuration Chain; 3.11.1 Memory Technologies for Configuration; 3.11.2 JTAG Interface
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 3.12 PLL and DLL3.12.1 Basic Structure and Operating Principle of PLL; 3.12.2 Typical PLL Block; 3.12.3 Flexibility and Restriction of PLL Blocks; 3.12.4 Lock Output; 3.12.5 DLL; References; 4 Design Flow and Design Tools; 4.1 Design Flow; 4.2 Design Flow by HDL; 4.2.1 Registration of Project; 4.2.2 Logic Synthesis and Technology Mapping; 4.2.3 RTL Simulation; 4.2.4 Place and Route; 4.2.5 Programming; 4.2.6 Verification and Debugging on Actual Device; 4.2.7 Optimization; 4.3 HLS Design; 4.3.1 Behavioral Description; 4.3.2 Behavior Level Simulation; 4.3.3 Behavioral Synthesis
505 8# - FORMATTED CONTENTS NOTE
Formatted contents note 4.3.4 Evaluation and Optimization4.3.5 Connection with RTL; 4.4 IP-Based Design; 4.4.1 IP and Its Generator; 4.4.2 Use of IP and Its Integration Tool; 4.4.3 Support Tool for Building IP; 4.5 Design with Processor; 4.5.1 Hard-Core Processor and Soft-Core Processor; 4.5.2 Building Processor System; 4.5.3 Software Development Environment; 4.5.4 Integration and Operation of Software and Hardware; References; 5 Design Methodology; 5.1 FPGA Design Flow; 5.2 Technology Mapping; 5.3 Clustering; 5.4 Place and Route; 5.5 Low Power Design Tools; 5.5.1 Emap: Low Power Consumption Mapping Tool
520 ## - SUMMARY, ETC.
Summary, etc. This comprehensive textbook on the field programmable gate array (FPGA) covers its history, fundamental knowledge, architectures, device technologies, computer-aided design technologies, design tools, examples of application, and future trends. Programmable logic devices represented by FPGAs have been rapidly developed in recent years and have become key electronic devices used in most IT products. This book provides both complete introductions suitable for students and beginners, and high-level techniques useful for engineers and researchers in this field. Differently developed from usual integrated circuits, the FPGA has unique structures, design methodologies, and application techniques. Allowing programming by users, the device can dramatically reduce the rising cost of development in advanced semiconductor chips. The FPGA is now driving the most advanced semiconductor processes and is an all-in-one platform combining memory, CPUs, and various peripheral interfaces. This book introduces the FPGA from various aspects for readers of different levels. Novice learners can acquire a fundamental knowledge of the FPGA, including its history, from Chapter 1; the first half of Chapter 2; and Chapter 4. Professionals who are already familiar with the device will gain a deeper understanding of the structures and design methodologies from Chapters 3 and 5. Chapters 6–8 also provide advanced techniques and cutting-edge applications and trends useful for professionals. Although the first parts are mainly suitable for students, the advanced sections of the book will be valuable for professionals in acquiring an in-depth understanding of the FPGA to maximize the performance of the device.
590 ## - LOCAL NOTE (RLIN)
Local note Master record variable field(s) change: 072
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Field programmable gate arrays.
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element TECHNOLOGY & ENGINEERING / Mechanical.
Source of heading or term bisacsh
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Circuits & components.
Source of heading or term bicssc
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronics engineering.
Source of heading or term bicssc
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Computer architecture & logic design.
Source of heading or term bicssc
650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic Design.
Authority record control number or standard number http://scigraph.springernature.com/things/product-market-codes/I12050
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Circuits and Systems.
Authority record control number or standard number http://scigraph.springernature.com/things/product-market-codes/T24068
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronic Circuits and Devices.
Authority record control number or standard number http://scigraph.springernature.com/things/product-market-codes/P31010
650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronics and Microelectronics, Instrumentation.
Authority record control number or standard number http://scigraph.springernature.com/things/product-market-codes/T24027
650 #7 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Field programmable gate arrays.
Source of heading or term fast
Authority record control number or standard number (OCoLC)fst00923910
655 #4 - INDEX TERM--GENRE/FORM
Genre/form data or focus term Electronic books.
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Amano, Hideharu,
Relator term editor.
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Printed edition:
International Standard Book Number 9789811308239
776 08 - ADDITIONAL PHYSICAL FORM ENTRY
Relationship information Printed edition:
International Standard Book Number 9789811308253
856 40 - ELECTRONIC LOCATION AND ACCESS
Materials specified EBSCOhost
Uniform Resource Identifier <a href="http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=1884181">http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=1884181</a>
850 ## - HOLDING INSTITUTION
Holding institution Kuakarun Nursing Library
938 ## -
-- EBL - Ebook Library
-- EBLB
-- EBL5507728
938 ## -
-- YBP Library Services
-- YANK
-- 15683585
938 ## -
-- EBSCOhost
-- EBSC
-- 1884181
994 ## -
-- 92
-- N$T
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type Electronic books
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Shelving location Date acquired Total Checkouts Barcode Date last seen Price effective from Koha item type
    National Library of Medicine Classification   Online Access Kuakarun Nursing Library Kuakarun Nursing Library Processing unit 31/08/2021   Eb33771 31/08/2021 31/08/2021 Electronic books